-- Contador de "2d" BCD

library ieee;
use ieee.std_logic_1164.all;
use work.PCT_COUNT_DEC_BCD.all;

entity COUNT_2_BCD is
port(
		CLK, CLR: in std_logic;
		PRESETS: in std_logic_vector(3 downto 0);
		QC4, QC3, QC2, QC1: out std_logic
	);
end COUNT_2_BCD;

architecture DT_FLOW of COUNT_2_BCD is
signal QNAND_CLR : std_logic; --:= '1';
signal QAND_CLR : std_logic; --:= '1';
signal QFF_T1 : std_logic; --:= '0';
signal QFF_T2 : std_logic; --:= '0';
signal QFF_T3 : std_logic; --:= '0';
signal QFF_T4 : std_logic; --:= '0';
signal ENTRADA : std_logic := '1';

begin
	AND_CLR: AND_2 port map (CLR, NOT(QNAND_CLR), QAND_CLR);
	FF_T1: FF_T port map (CLK, QAND_CLR, PRESETS(0), ENTRADA, QFF_T1);
	FF_T2: FF_T port map (QFF_T1, QAND_CLR, PRESETS(1), ENTRADA, QFF_T2);
	FF_T3: FF_T port map (QFF_T2, QAND_CLR, PRESETS(2), ENTRADA, QFF_T3);
	FF_T4: FF_T port map (QFF_T3, QAND_CLR, PRESETS(3), ENTRADA, QFF_T4);
	--NAND_CLR: NAND_2 port map (QFF_T1, QFF_T2, QNAND_CLR);
	QNAND_CLR <= QFF_T1 AND QFF_T2 AND NOT(QFF_T3) AND NOT(QFF_T4);
	
	QC4 <= QFF_T4;
	QC3 <= QFF_T3;
	QC2 <= QFF_T2;
	QC1 <= QFF_T1;
	
end DT_FLOW;